The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials, design, and fabrication tools have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of these advances, fabrication methods have been developed to realize the desire for smaller feature sizes. For example, methods have been developed that reduce the pitch of features on a substrate without changing the photolithography technology used.
These methods and technological advances give rise to challenges however. For example, alignment between layers of an IC becomes both more critical, and more difficult, as the technology node decreases. Thus, what is desired is a device and method to allow for reduced pitch of features, while maintaining an alignment with an overlying feature.